1. Field of the Invention
The present invention relates to a semiconductor device and its fabricating method, and particularly to a semiconductor element isolating structure and its fabricating method.
2. Description of the Background Art
First, the construction of a prior art semiconductor device will be described with reference to the drawings.
FIG. 24 is a schematic sectional view showing the construction of a prior art semiconductor device. Referring to FIG. 24, an isolating oxide film 5 is formed on the surface of a p-type silicon substrate 1 in an element isolating region 60. An nMOS (Metal Oxide Semiconductor) transistor 20 is formed in an element forming region 50 isolated by the isolating oxide film 5.
The nMOS transistor 20 includes a pair of source/drain regions 11, a gate oxide film 15 and a gate electrode layer 17. A pair of the source/drain regions 11 are formed on the surface of the p-type silicon substrate 1 in such a manner as to be separated from each other at a specified distance. The source/drain region 11 has a double structure of an n.sup.- impurity diffusion region 7 doped with an n-type impurity at a relatively low concentration and an n.sup.+ impurity concentration region 9 doped with an n-type impurity at a relatively high concentration, that is, it has an LDD (Lightly Doped Drain) structure. A gate electrode layer 17 is formed, by way of a gate oxide film 15, on a region surrounded by a pair of the source/drain regions 11.
The source/drain region 11 having an LDD structure is effective to relax a field intensity in the channel direction near the drain region, and hence to suppress the generation of hot-electrons. The source/drain region 11 is adjacent to the isolating oxide film 5. In addition, a side wall insulating layer 19 is formed for covering the side wall of the gate electrode layer 17.
A p.sup.+ impurity diffusion region 3 is formed within the p-type silicon substrate 1 in such a manner as to be contacted with the lower surface of the isolating oxide film 5 in the element isolating region 60 and to be positioned near the lower side of the nMOS transistor 20 in the element forming region 50. The p-type impurity concentration of the p.sup.+ impurity diffusion region 3 is set to be higher than that of the p-type silicon substrate 1. The p.sup.+ impurity diffusion region 3 has the peak of the p-type impurity concentration along the dotted line 3a. The p.sup.+ impurity diffusion region 3 and the element isolating oxide film 5 function to electrically isolate the nMOS transistor 20 from other elements.
FIGS. 25, 26 are diagrams each showing a change in carrier concentration relative to a change in depth along each of lines C.sub.5A -C.sub.5B and D.sub.5A -D.sub.5B of FIG. 24. Referring to FIGS. 25, 26, in the prior art semiconductor device, the p-type impurity concentration of the p-type silicon substrate 1 is substantially 1.times.10.sup.15 cm.sup.-3 ; and the p-type impurity concentration of the p.sup.+ impurity diffusion region 3 is in the range of from 1.times.10.sup.17 cm.sup.-3 to 1.times.10.sup.18 cm.sup.-3. On the other hand, the n-type impurity concentration of the n.sup.+ impurity diffusion region 9 is less than 1.times.10.sup.20 cm.sup.-3, and the n-type impurity concentration of the n.sup.- impurity diffusion region 7 is in the range of from 1.times.10.sup.17 cm.sup.-1 to 1.times.10.sup.18 cm.sup.-3.
Next, a method of fabricating a semiconductor device shown in FIG. 24 according to the prior art will be described.
FIGS. 27 to 34 are schematic sectional views showing processes of fabricating a semiconductor device according to the prior art in sequence.
Referring to FIG. 27, a thin silicon oxide film 21 is formed over the whole surface of a p-type silicon substrate 1. A silicon nitride film 23 is formed over the whole surface of the thin silicon oxide film 21.
Referring to FIG. 28, a photoresist 25 is applied over the whole surface of the silicon nitride film 23. The photoresist 25 is patterned by exposure. The silicon nitride film 23 is patterned using the patterned photoresist 25 as a mask. After that, the resist pattern 25 is removed.
Referring to FIG. 29, a portion exposed from the silicon nitride film 23 is selectively oxidized by LOCOS (Local Oxidation of Silicon) using the silicon nitride film 23 as a mask. An isolating oxide film 5 is formed on the surface of the p-type silicon substrate 1 by this selective oxidation. After that, the silicon nitride film 23 and the thin silicon oxide film 21 on the surface of the p-type silicon substrate 1 are sequentially removed by etching.
Referring to FIG. 30, ions of boron (B) are implanted in the whole surface of the p-type silicon substrate 1. With this ion implantation, a p.sup.+ impurity diffusion region 3 is formed within the p-type silicon substrate 1 in such a manner as to be positioned near the lower side of the isolating oxide film 5 in the element isolating region and to be positioned at a specified depth from the surface of the p-type silicon substrate 1. In addition, the impurity concentration of the p.sup.+ impurity diffusion region 3 is set to be higher than that of the p-type silicon substrate 1.
Referring to FIG. 31, a thin silicon oxide film 15 is formed on the exposed surface of the p-type silicon substrate 1 by thermal oxidation or the like. A polycrystalline silicon layer 17 is formed over the whole surface of the p-type silicon substrate 1.
Referring to FIG. 32, the polycrystalline silicon layer 17 and the thin silicon oxide film 15 are sequentially patterned by photolithography, RIE (Reactive Ion Etching) or the like. A gate electrode layer 17 and a gate oxide film 15 are thus formed. Ions of phosphorous (P) are implanted over the whole surface of the p-type silicon substrate 1 using the gate electrode layer 17 and the isolating oxide film 5 as a mask. With this ion implantation, a pair of n.sup.- impurity diffusion regions 7 are formed on the surface of the p-type silicon substrate 1 in such a manner as to surround the lower region of the gate electrode layer 17.
Referring to FIG. 33, a silicon oxide film is formed over the whole surface of the p-type silicon substrate 1, and then the silicon oxide film is subjected to anisotropic etching. With this etching, a side wall insulating layer 19 is formed in such a manner as to cover the side wall of the gate electrode layer 17.
Referring to FIG. 34, ions of arsenic (As) are implanted in the whole surface of the p-type silicon substrate 1 using the side wall insulating layer 19, gate electrode layer 17 and the isolating oxide film 13 as a mask. With this ion-implantation, a pair of n.sup.+ impurity diffusion regions 9 are formed in such a manner as to surround the lower regions of the gate electrode layer 17 and the side wall 19. An n-type source/drain region 11 having an LDD (Lightly Doped Drain) is formed of the n.sup.+ impurity diffusion region 9 and the n.sup.- impurity diffusion region 7.
An nMOS transistor 20 is formed of a pair of the source/drain regions 11, gate oxide film 15 and gate electrode layer 17.
In addition, "n.sup.+ " means a relatively high concentration of an n-type impurity, and "n.sup.- " means a relatively low concentration of an n-type impurity. 0n the other hand, "p.sup.+ " means a relatively high concentration of a p-type impurity, and "p.sup.- " means a relatively low concentration of a p-type impurity.
As is well-known, in the LOCOS structure, when the isolating oxide film 5 is formed, crystal defects 50 are generated near the interface between the p-type silicon substrate 1 and the isolating oxide film 5 as shown in FIG. 24, and they tend to cause leakage current; and the leakage current flowing by way of the crystal defects 50 is increased when the crystal defects 50 are distributed in a depletion layer at the pn-junction constituted of the n-type source/drain region 11 and the p-type silicon substrate 1. This is described, for example in Sugano, Ono and Usui, editor: "MOS Field Effect Transistor", Nikkan Kogyo, p219 and Solid-State Electronics, Vol. 9, 1966, pp783-806.
For this reason, it is necessary to design an impurity distribution for suppressing the extension of a depletion layer at the pn-junction. Such an impurity distribution is disclosed in Unexamined Japanese Patent Laid-Open No. 2-133929. The construction disclosed in this reference will be described below.
FIG. 35 is a schematic sectional view showing the construction of a semiconductor device shown in the above-described reference. Referring to FIG. 35, an isolating oxide film 305 is selectively formed on the surface of a silicon substrate 310. A p.sup.+ channel cut region 303 is formed within the p-type silicon substrate 301 in such a manner as to be positioned near the lower side of the isolating oxide film 305. An nMOS transistor 320 is formed in an element forming region isolated by the isolating oxide film 305 and the p.sup.+ channel cut region 303.
The nMOS transistor 320 has a pair of source/drain regions each having portions 307, 309, 313, a gate insulating film 315, and a gate electrode layer 317. A pair of the source/drain regions each having the portions 307, 309, 313 are formed on the surface of the p-type silicon substrate 301. The gate electrode layer 317 is formed, by way of the gate insulating film 315, on a region surrounded by a pair of the source/drain regions.
In the construction of the semiconductor device disclosed in the above reference, the source/drain region has the portions 307 and 309 constituting an LDD structure, and a portion 313 for preventing leakage current due to crystal defects. Specifically, the n-type impurity diffusion region 313 is provided at the side end portion of the isolating oxide film 305, so that crystal defects formed near the interface between the p-type silicon substrate 301 and the isolating oxide film 305 upon formation of the isolating insulating film 305 are contained in the n-type impurity diffusion region 313. This makes it possible to suppress the crystal defects introduced at the side end portion of the isolating oxide film 305 from being distributed in a depletion layer upon operation of the nMOS transistor, and hence to prevent the generation of leakage current due to the distribution of crystal defects at the side end portion of the isolating oxide film 305 in a depletion layer. The characteristics of the element can be thus improved.
The construction of the above-described reference shown in FIG. 35 is disadvantageous in that: (1) circuit operation is delayed, and (2) element isolating ability is low.
(1) Delay in Circuit Operation
In the semiconductor device shown in FIG. 35, the n-type impurity diffusion region 313 is added for preventing the generation of leakage current due to crystal defects; however, by the addition of the n-type impurity diffusion region 313, the area of the pn-junction between the p-type silicon substrate 301 and the n-type source/drain region is enlarged. As a result, the junction capacity at the pn-junction is increased, which leads to delay in circuit operation.
(2) Reduction in Element Isolating Ability
FIG. 36 is a schematic sectional view showing the construction in which a plurality of the semiconductor devices shown in FIG. 35 are formed. Referring to FIG. 36, a gap L.sub.2 between the n-type source/drain regions of the adjacent nMOS transistors 320 is reduced by the addition of the n-type impurity diffusion region 313. Namely, in the case where the n-type impurity diffusion region 313 is not provided, a gap L.sub.1 between the n-type source/drain regions of the adjacent nMOS transistors 320 is substantially the same as the width of the isolating oxide film 305. On the contrary, in the case where the n-type impurity diffusion region 313 is provided, the gap L.sub.2 between the adjacent n-type source/drain regions is made narrower than the width of the isolating oxide film 305. As a result, the electrically isolating ability is reduced between the n-type source/drain regions of the adjacent nMOS transistors.